The invention relates to the field of debugging multiprocessor systems, and particularly to the area of reproducing an application execution which encounters an error situation. The error situation could be from hardware or software.
A multiprocessor system includes a large number of processor chips and other chips. Various factors make it difficult for a multiprocessor system to offer reproducibility. For example, the signalling between chips in a multiprocessor system is today typically based on high-speed signalling techniques where the transit time of data is much longer than the effective “bit time” of the transmission. Such an asynchronous interconnect does not easily offer reproducibility.
Without reproducibility, a multiprocessor system instead typically offers other methods to assist in their debugging. Multiprocessor systems to date thus typically offer elaborate hardware checking mechanisms which are often complex, expensive in terms of effort and silicon cost and power, and generally do not address all potential debugging situations. An example of such a hardware checking mechanism is a trace buffer which can record some of the past actions of the hardware.
One document that deals with reliability in power PC's is M. Abbott et al. “Durable Memory RS/6000™ System Design” The 24th Annual International Symposium on Fault Tolerant Computing FTCS-24 1 Austin, Tex., USA; Jun. 15-17, 1994 the contents and disclosure of which are incorporated by reference as if fully set forth herein.